A 54–64-GHz 4TXs-4RXs CMOS Transceiver With 10-GHz Bandwidth Single Chirp for FMCW Radar Applications

This article presents a 54–64-GHz CMOS transce- iver with four transmitters (4TXs) and four receivers (4RXs). This transceiver is able to generate continuous and single 10-GHz bandwidth chirp signals for frequency-modulated continuous wave (FMCW) radar. Dual-supply phase-locked loop (PLL), low-noise amplifier (LNA) with low-coupling factor transformer, and four-stage power amplifier (PA) with capacitive neutralization technique are designed to realize a 10-GHz bandwidth chirp. The voltage-controlled oscillator (VCO) operation range is from 26.9 to 32.54 GHz. The VCO phase noise is −93 dBc/Hz at a 1-MHz offset frequency from a 30-GHz carrier frequency. The averaged in-band phase noise of the PLL in operating frequency band is −67.4 dBc/Hz at 100 kHz offset frequency. The TXs, including 6-bit phase shifters, achieve a 9.63-dBm saturated output power and OP 1 dB of 6.75 dBm for each channel. The LNA achieves a return loss of less than 6.4 dB over the 54–64 GHz operating range. The RX overall gain, including the integrated analog baseband (ABB) with two-stage bi-quad bandpass filters (BPFs) is 80 dB, and noise figure (NF) is 11.6 dB. The proposed transceiver consumes 731.3 mA when operating all channels. This chip occupies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 3.4$ </tex-math></inline-formula> mm2 and was fabricated in 65-nm CMOS technology.