Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications

Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption ( ∼ 12 × ), layout area ( ∼ 5 × ), and latency ( ∼ 1 . 4 × ) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.