Hybrid Logic Style CMOS Full Adder Using 10-T XOR & XNOR Circuit

The hybrid CMOS full adder (FA) architecture is described in the paper and detailed working principles based on hybrid logic structure of 10 transistors XOR and XNOR circuit. The XOR and XNOR circuitry provide active outputs. Where, CMOS full adder (FA) circuit entire working stage depends on XOR and XNOR outputs. The technology used for this proposed methodology is 0.45nm CMOS technique to simulate output through GPDK "Cadence virtuoso Tool". In this proposed research the overall full adder propagation delay, Power consumption and switching Energy significantly reduced.