Enhancing the Lifetime of STT-RAM by IFTRP

Abstract Spin Transfer Torque Random Access memory (STT-RAM) is a better
 alternative to overcome the shortcomings of the existing memory tech
nologies. But, the implementation of STT-RAM memory technologies on
 the existing memory are limited due to its write restriction. The dis
advantages of STT-RAM have been overcome by many of the existing
 techniques. The existing techniques either reduce the writes or variation
 in the writes on the cache block in inter-set(IeS) or intra-set(IrS) by writ
ing the data from hot block to cold block, which may lead to a Repeated
 Address Attack. A IFTRP (Inter-secure Fault Tolerant Replacement Pol
icy) is proposed to reduce the attacks and have lifetime enhancement on
 the STT-RAM. The variation in writes is reduced by IFTRP in both IeS
 and IrS by RSS (Randomized Swap Shift policy), RICL(Randomized In
validation Cache Line) method with a variation in the threshold values,
 so that the location of data blocks is not predictable by the intruder. The
 proposed method also identifies the partial cell failures by flagging them
 as invalid, so that the future write is not performed on the invalid line.
 The proposed method reduces the attacks and improves the lifetime of
 the memory by 15% in cache and has negligible area overhead.