Analysis of a low-dropout voltage regulator designed using omega-gate nanowire transistors experimental data

In this work, the low-dropout voltage regulator (LDO) was designed using omega-gate nanowire transistors. These transistors were modeled using the Verilog-A description based on the experimental data. After the model validation LDO’s were developed using gm/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> strategy considering transconductance over drain current ratio (gm/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf>) of 7V<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> and 8V<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> with load capacitances of 10pf and 100pf. The LDO was designed to provide a voltage of 1.5V and 100μA at the output. The LDO biased transistors with gm/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> equal to 8V<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> presented very good results where the Loop Voltage Gain was 52.2dB, the gain bandwidth product (GBW) was 5.9MHz for load of 10pf, the load regulation was 27V/A and power supply rejection (PSR) was 41dB showing that Omega-gate nanowire transistors can be a good option for LDOs circuits.