An Online Unified Delay and Slew Rate Regulation for Current Sharing in Paralleled SiC Power Modules With Active Gate Drivers

To ensure balanced current sharing between paralleled power modules, active gate drivers (AGDs) can be used to adjust the currents dynamically. However, achieving effective, flexible and accurate dynamic current adjustment is a challenge for AGDs under the very fast switching speed of silicon carbide (SiC) devices, e.g., <100 ns. Therefore, an online unified turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>/<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> delay and current slew rate regulation scheme for AGDs for paralleling SiC metal-oxide-semiconductor field-effect-transistor (MOSFET) power modules is proposed in this article. The advantage of the proposed scheme is that it achieves independent closed-loop control for the delay regulation and the current slew rate regulation, i.e., the adjustment of the current slew rate will not affect the already-tuned delay compensation. Also, the proposed AGD based on gate resistance adjustment with just two push–pull driver channels and less switching actions can achieve the wider-range and multilevel current slew rate regulation. Experimental validation of the closed-loop current regulation for current sharing between SiC power modules with the presented AGD is provided.