Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min-Max Algorithm

Considered a next-generation error-correction solution, non-binary low-density parity-check (NB-LDPC) codes exhibit remarkable correcting capabilities, outperforming binary counterparts for severe channel conditions. However, contemporary decoder designs encounter challenges due to the demanding hardware resources required by their high processing complexity. In this work, we propose a novel column-wise trellis min-max (CW-TMM) algorithm, which significantly reduces the sorter overheads in the existing TMM method without degrading the error-correcting power. We also deploy the message compression to the trellis-based algorithm for effectively reducing hardware costs, even allowing the storage-aware long codes by accommodating large-sized on-chip memories. Through the integration of advanced low-cost optimization schemes together, the prototype CW-TMM decoder in a 28-nm CMOS technology for 4-kB 0.9-rate NB-LDPC codes demonstrates a 54% reduction in on-chip memory size and a 63% decrease in decoding complexity, enhancing the area efficiency by more than 2.4 times than the state-of-the-art approaches.