Improving Single-Event Effect Performance of SiC MOSFET by Excess Hole Extraction

Heavy ion strike-induced Single-Event Effect (SEE) is an essential reliability issue for SiC MOSFETs in radiation environments. The mass clustering of excess charges in SiC MOSFET is found to be root cause for device failure when heavy ion strikes. Based on the SEE failure mechanism, a planar gate SiC MOSFET with Hole Extraction Channel (HEC-MOS) and current aperture structure to improve its SEE immunity and electrical performance is proposed in this paper. The embedded <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P^{+}$ </tex-math></inline-formula> pillar provides an additional path to extract excess holes during heavy ion radiation so that transient currents and SEE response time are greatly reduced. As a result, the maximum lattice temperature (hot spot) decreases by 768K, and a single-event burnout (SEB) threshold voltage of 624V is achieved with linear energy transfer (LET) value of 75MeV<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>cm2/mg for HEC-MOS, which is 1.4 times higher than conventional SiC MOSFET (Conv-MOS). Moreover, the gate oxide electric field also decreases ~10 times owing to much less clustered holes in JFET region, which ensures HEC-MOS superior immunity to single-event gate rupture (SEGR). Apart from improving SEE performance, a better trade-off with its electrical performances is also considered. By adopting optimized parameters in current spreading layers and P+ pillar, the specific ON-resistance of HEC-MOS is reduced by 17.5% while maintain a good forward blocking capability and SEB immunity. Therefore, HEC-MOS is a promising candidate for harsh environmental applications.