A High dimensional and high sigma statistical model for SRAM read access yield estimation

Statistical analysis for the yield of large-scale circuits is quite difficult due to expensive simulations, especially for the memory circuits with high sigma requirement (e.g., SRAM). In this paper, we developed an efficient sparse additive model to substitute simulations. To fit high sigma region accurately, the modeling center is moved to near failure boundary searched by scaling the shape of sampling function. To solve the model efficiently, the process variables are grouped by standard cells so that the model can be solved by our developed blockwise greedy algorithm. The experiments on the 28nm memory circuits validate that our method achieves high accuracy and efficiency compared with other state-of-art works.