Design and Implementation of High Throughput and Efficient FIR Filter Architectures using Unfolding

The unfolding technique can be used to generate word-level parallel processing architectures as it uses fewer clock cycles to compute an output sample. This paper aims to design and implement word-level parallel processing architectures for 2-tap, 4-tap and 11-tap serial low-pass FIR (Finite Impulse Response) filters. To improve the throughput of the proposed architectures, data broadcast types serial FIR filters were used. An unfolding factor with the value of two is taken for designing 2-unfolded architectures for the original serial FIR filter architectures. Proposed 2-unfolded architectures operate at 1200 KHz, and inputs for 2-unfolded architectures are generated by a serial-to-parallel converter circuit at a frequency of 2400KHz. FPGA (Field Programmable Gate Array) system clock is used to generate these frequencies. VHDL (Very High Speed Integrated Circuit HDL) language is used to design 2- unfolded architectures, and Xilinx Vivado 2015.2 tool is used to implement these architectures on the Artix7 Basys3 FPGA board. Designed and implemented 2-unfolded architectures are compared with existing serial and parallel FIR filter architectures.