Design and Analysis of High-Speed Sub-Threshold Operating Voltage Domino Logic

The development and application of CMOS VLSI semiconductor circuits employing sub-micron technology has faced significant challenges, specifically related to issues of latency and power usage. This paper presents the HSSODL technique, a novel approach for designing CMOS logic gates that minimize leakage current. The goal of this methodology has been to minimize energy consumption due to leakage while also improving digital circuit efficiency in terms of distortion. The suggested technique is utilized to create 16-bit OR gates, which are then simulated with Cadence's CMOS 45nm technology. The simulation results were evaluated by comparing Unity Noise Gain (UNG), power utilization, and latency. The findings from the simulation demonstrate that the suggested domino logic technique decreases the latency by a minimum of 35%. Overall, power usage and energy dissipation are lower than in contemporary domino logic techniques.