Software-Assisted Event Builder for Belle II Experiment

In this article, we present the design of the hybrid event builder algorithm for Belle II DAQ. The event builder is implemented in PCIe40 field-programmable gate array (FPGA) boards and reads up to 48 127 MB/s channels per board. The first version of the event builder implemented the algorithm entirely in the firmware of the FPGA. But due to limited onboard memories, there are hard limitations on the operation conditions. The new algorithm uses independent event processing for each channel in FPGA and a highly optimized readout software for final event building. This allowed us to increase the throughput of the system from 600 MB/s to 7.25 GB/s on a readout computer with 20 CPU cores. We successfully use the system to take data at trigger rates of up to 5.5 kHz in run 2 of Belle II experiment since February 2024.

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Publication Details

Journal
IEEE Transactions on Nuclear Science
Published
2024-09-17
DOI
https://doi.org/10.1109/tns.2024.3462595
Primary Topic
Scientific Computing and Data Management
Type
article
Field-Weighted Citation Impact
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article

Software-Assisted Event Builder for Belle II Experiment

K. Nishimura, S.-H. Park, M. Taurigna, S. Yamada et al.
IEEE Transactions on Nuclear Science
Scientific Computing and Data Management
article

Software-Assisted Event Builder for Belle II Experiment

K. Nishimura, S.-H. Park, M. Taurigna, S. Yamada, D. Charlet, R. Itoh, T. Kunigo, Q. Zhou, M. Bessner, D. Biswas, E. Plaige, Y.-T. Lai, H. Purwar, D. Levit, G. Varner, M. Nakao, P. Kapusta, P. Robbe, T. S. Lau, S. Y. Suzuki, E. Jules, T. Higuchi
article en

Abstract

In this article, we present the design of the hybrid event builder algorithm for Belle II DAQ. The event builder is implemented in PCIe40 field-programmable gate array (FPGA) boards and reads up to 48 127 MB/s channels per board. The first version of the event builder implemented the algorithm entirely in the firmware of the FPGA. But due to limited onboard memories, there are hard limitations on the operation conditions. The new algorithm uses independent event processing for each channel in FPGA and a highly optimized readout software for final event building. This allowed us to increase the throughput of the system from 600 MB/s to 7.25 GB/s on a readout computer with 20 CPU cores. We successfully use the system to take data at trigger rates of up to 5.5 kHz in run 2 of Belle II experiment since February 2024.

IEEE Transactions on Nuclear ScienceVol. 72(3)
University of Hawaiʻi at Mānoa (US), Centre National de la Recherche Scientifique (FR), High Energy Accelerator Research Organization (JP), Shandong University (CN), Kavli Institute for the Physics and Mathematics of the Universe (JP), University of Siegen (DE), Université Paris-Saclay (FR), Institute of Nuclear Physics, Polish Academy of Sciences (PL), Institut National de Physique Nucléaire et de Physique des Particules (FR), Laboratoire de Physique des 2 Infinis Irène Joliot-Curie (FR), The University of Tokyo (JP)
Openalex Percentile: Top 83%
Scientific Computing and Data Management
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