A Three-Fine-Level Buck–Boost Hybrid Converter Achieving Half-V_IN-Stress on All Switches and Fast Transient Response

This article presents a non-inverting three-fine-level buck-boost (3FLBB) hybrid converter suitable for lithium-ion (Li-ion) batteries. With seven power switches and two flying capacitors, the proposed 3FLBB converter produces the voltage of switching node between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {IN}}$ </tex-math></inline-formula>/2, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {IN}}$ </tex-math></inline-formula>, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3{V_{\mathrm {IN}}}$ </tex-math></inline-formula>/2, which supports buck, boost, and buck-boost modes, and with smooth mode changes. Here, one of the two flying capacitors is used to drive the inductor (L), while another one is used to ensure that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DS}}$ </tex-math></inline-formula> of each power switch is within 1/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{V_{\mathrm {IN}}}$ </tex-math></inline-formula> in all phases. Hence, the voltage stress of all the power switches is reduced to half-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {IN}}$ </tex-math></inline-formula>, and the normalized equivalent resistance and switching losses are greatly reduced by using two 1.8-V switches instead of two 5-V switches. Since the three modes all have buck-like operation, the average inductor current is reduced to always equal to the output current. Meanwhile, they all have continuous output current, similar complex pole pairs, and no right half-plane (RHP) zero, which enables fast load transient response. This design is implemented by only 1.8-V devices of a standard 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS process, covering an input voltage range from 2.8 to 4.2 V. A 98.<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</small>% peak efficiency is measured at 2-MHz switching frequency with 2.2-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>H L, two 10-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>F flying capacitors, and one 10-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>F output capacitor. It can deliver an output current of 50–1000 mA at a 3.3-V regulated output voltage. Moreover, the measured results show that this design achieves a significant improvement on undershoot and overshoot voltage than the previous works.