Study for the Linearity Improvement of ㎓-band Low Noise Amplifier

This paper presents a case study on enhancing the linearity of ㎓-band low noise amplifiers (LNAs). Given the potential for large interference signal tones at the receiver end along with the carrier, the LNA is expected to provide high linearity, thus preventing the intermodulation tones created by the interference signal from corrupting the carrier signal. To verify this study, we designed a LNA using a 0.18㎛ BiCMOS process and a three-type LNA using a 65㎚ CMOS process. We analyzed a four-type LNA for the case study of the linearity by adopting a MOS-BJT derivative superposition (MBDS) technique, a built-in linearizer structure, a cascode structure, and a CG NMOS-PMOS inverter scheme. The LNA using the 0.18㎛ BiCMOS and MBDS technique achieved the highest IIP3 and OIP3 of 20 ㏈m and 42 ㏈m at 2.4 ㎓, respectively. The LNA with the NMOS-NMOS cascode structure also demonstrated excellent IIP3 and OIP3 values of 5 ㏈m and 21.8 ㏈m at 24 ㎓, respectively.