Automated Feature Testing of Verilog Parsers using Fuzzing (Registered Report)

In this article we propose a methodology based on fuzzing to test which features are supported by pasers and register an experiment applying this methodology to SystemVerilog-consuming tools. SystemVerilog is a hardware description, specification and verification language widely used in hardware design, and with an active standard committee. Most SystemVerilog-consuming tools have incomplete support and support additional features. These tools do not provide the list of features they support, so identifying commonly supported SystemVerilog features is complicated. This hinders design portability and tool interoperability. We think current efforts to test these tools' feature support are insufficient. All of the previous points justify why SystemVerilog-consuming tools are a good candidate for our methodology. We also provide the first (to our knowledge) open-source parser and fuzzer for Verilog with full support and compliance with the 2005 standard.