Point Multiplication Acceleration Over Edwards25519 Using FPGA

Point multiplication is the most expensive operation in ECC as it repetitively utilizes field multiplication. In this research, we propose an efficient FPGA-based point multiplication over Edwards25519. The majority of the enhancements stem from the invention of a novel field multiplier and the implementation of three general rules to achieve optimal scheduling of operations in the point multiplication. First, field multiplications with the longest path are given the highest precedence. Second, field multiplications with a greater number of output edges are given higher precedence. Third, priority is given to the field multiplications that compute the final outputs. The innovative field multiplier is based on the Karatsuba–Ofman multiplication method, which involves four steps. This multiplier uses fewer additions and subtractions than the original numbers. Additionally, it features a semi-systolic architecture with a few register layers, resulting in low CPD and latency. Compared to the most efficient previous work, the proposed point multiplication is 139% more efficient and 7% faster.