A Bandwidth Extension Technique for Improving Jitter in Ring-VCO-Based Sub-Sampling PLLs

This brief proposes a structure to enhance the bandwidth of type-I sub-sampling phase-locked loops (SSPLL) without compromising the loop stability. A voltage-controlled delay line (VCDL) is employed at the output of the voltage-controlled oscillator (VCO) to readjust the phase of the VCO. The delay of this VCDL is controlled based on the instantaneous phase of the VCO, extracted at the output of the phase detector. Using theoretical analysis and simulations, it is proved that the bandwidth of the VCO phase noise to the output phase noise transfer function can increase up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {0.4f_{\text {REF}}}$ </tex-math></inline-formula> while maintaining phase margin. This enhanced bandwidth improves the VCO phase noise filtering strength of the PLL, leading to a superior jitter performance. The phase-domain model reveals a significant reduction in integrated jitter, compared to conventional type-I and type-II SSPLL, respectively. Furthermore, it is shown that the jitter reduction capability in the proposed loop remains robust against temperature and process variations.