PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications
▪Coarse-grained reconfigurable arrays (CGRAs) deliver high energy efficiency while maintaining the programmability advantages. ▪CGRA is the ideal candidate for efficiently handling loop kernels, which allows it to offload repetitive looping functions such as vector multiplication or hashing algorithms from CPUs. ▪It relies on a compiler to convert a given workload into a data flow graph (DFG) which is then mapped onto the hardware in a manner that achieves the highest possible energy efficiency.
Authors
- Yi Sheng Chong (ORCID: https://orcid.org/0000-0003-4136-6570)
- Thilini Kaushalya Bandara (ORCID: https://orcid.org/0000-0003-3413-136X)
- Vishnu P. Nambiar (ORCID: https://orcid.org/0000-0001-5570-5911)
- Zhaoying Li (ORCID: https://orcid.org/0000-0001-7513-9494)
- Tulika Mitra (ORCID: https://orcid.org/0000-0003-4136-4188)
- Li-Shiuan Peh (ORCID: https://orcid.org/0000-0001-9010-6519)
- Rohan Juneja (ORCID: https://orcid.org/0000-0002-6015-1084)
- Dhananjaya Wijerathne (ORCID: https://orcid.org/0000-0003-3181-2514)
- Anh Tuan (ORCID: https://orcid.org/0000-0002-8320-6818)
Institutions
- Agency for Science, Technology and Research (SG)
- National University of Singapore (SG)
- Institute of Microelectronics (SG)
Publication Details
- Published
- 2024-08-25
- DOI
- https://doi.org/10.1109/hcs61935.2024.10665106
- Citations
- 3
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.63
Funders
- National Research Foundation Singapore