CogniVision: A mW Power envelope SoC for Always-on Smart Vision in 40nm

A full vision system on chip with hierarchical execution from sensor to AI and communications is presented. Always-on system power is aggressively reduced to the mW level through activity reduction, gating any subsequent vision pipeline stage starting from the lowest semantic level of the scene. The system comprises an imager with dual-architecture in/near-sensor saliency detection, on the-fly novelty detection, DNN accelerator with on-chip scheduler for weight memory reduction, WiFi transmitter, wake-up receiver for cloud pushed DNN model update and software programmable orchestration via RISC-V. Average 2.1-mW power at 30 fps is achieved with a SqueezeNet V1.0 model running entirely on chip.