An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm

In this brief, an improved and efficient Winograd-based Large Integer Multiplication using least-positive form named WLIM is proposed, which can reduce 28.61% to 33.33% of the number of multiplications compared to least-positive form direct multiplication. By exploiting the cyclic parallelism of the improved algorithm, an Efficient and Parallelism-Scalable Large Integer Multiplier architecture named EPSM is proposed, which has two levels of adjustable parallelism. EPSM is implemented on Xilinx Virtex-7 VC709 Board, Zynq UltraScale+ XZCU19EG Device, and Alveo U250 Card, by using Vivado. Compared with the related works, EPSM can achieve a performance improvement of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.29\times \sim ~20.99\times $ </tex-math></inline-formula>. In terms of area efficiency, EPSM can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.54\times \sim ~41.41\times $ </tex-math></inline-formula> area-time product (ATP) improvements.

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Publication Details

Journal
IEEE Transactions on Circuits & Systems II Express Briefs
Published
2024-09-10
DOI
https://doi.org/10.1109/tcsii.2024.3457494
Citations
1
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
0.49

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article

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm

Jia Hou, Yishuo Meng, Fahong Zhang, Jianfei Wang et al.
1 citations
IEEE Transactions on Circuits & Systems II Express Briefs
Parallel Computing and Optimization Techniques
0.49
article

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm

Jia Hou, Yishuo Meng, Fahong Zhang, Jianfei Wang, Chen Yang, Yang Su
article en
1 citations

Abstract

In this brief, an improved and efficient Winograd-based Large Integer Multiplication using least-positive form named WLIM is proposed, which can reduce 28.61% to 33.33% of the number of multiplications compared to least-positive form direct multiplication. By exploiting the cyclic parallelism of the improved algorithm, an Efficient and Parallelism-Scalable Large Integer Multiplier architecture named EPSM is proposed, which has two levels of adjustable parallelism. EPSM is implemented on Xilinx Virtex-7 VC709 Board, Zynq UltraScale+ XZCU19EG Device, and Alveo U250 Card, by using Vivado. Compared with the related works, EPSM can achieve a performance improvement of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.29\times \sim ~20.99\times $ </tex-math></inline-formula>. In terms of area efficiency, EPSM can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.54\times \sim ~41.41\times $ </tex-math></inline-formula> area-time product (ATP) improvements.

IEEE Transactions on Circuits & Systems II Express BriefsVol. 72(1)
Chinese People's Armed Police Force Engineering University (CN), Xi'an Jiaotong University (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 38%
Parallel Computing and Optimization Techniques
0.49
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An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm — Jia Hou, Yishuo Meng, et al. · IEEE Transactions on Circuits & Systems II Express Briefs (2024) | TGRS Research Map | TGRS