A <i>V</i>-Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700 nW

This article presents and investigates a V-band transmitter (TX) for low-power wireless communication supporting ON-OFF keying (OOK) and four-/eight-level pulse amplitude modulation (PAM4/8). To prove the concept, the circuit is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) complementary metal oxide semiconductor (CMOS) technology. The TX consumes 11.7 mW at full speed. Furthermore, the TX supports low-power mode with as low as 700 nW of dc power. The maximum data rate is 2 Gb/s. By applying dynamic data rate to dc-power adaptivity (DDDA), the dc power can be significantly reduced as the data rates decreases. This maintains the energy-per-bit below 10 pJ/b for data rates greater than 100 kb/s with a best value of 3.9 pJ/b and allows the dc power to be greatly reduced down to 700 nW at data rates below 20 kb/s. The measured maximum transmission power is 6.5 dBm. Moreover, the TX achieves 10- dBm effective isotropic radiated power (EIRP) with an on-chip 3-D antenna. The core area of the TX is only 0.19 mm2. To the best knowledge of the authors, the proposed TX is the first reported TX with DDDA and achieves the lowest dc power in comparison to similar designs that have been reported to date.