SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-Low Power Loss and Improved Short-Circuit Capability

A silicon carbide (SiC) double trench metal-oxide-semiconductor field effect transistor (DTMOS) with split gate (SG) and integrated Schottky barrier diode (SBD) is proposed for the first time. The proposed device features two enhanced deep trenches in the surface, in which a source-connected SG with a thicker dielectric layer is located at the bottom of the deep gate trench and an integrated SBD is located at the sidewall of the deep source trench (DST). Combined with shielding effect provided by the P<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> shield layer under the DST and integrated SBD, the proposed structure not only reduces the reverse transfer capacitance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C_{\text{rss}})$</tex> and gate-drain charge <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(Q_{\text{gd}})$</tex> but also restrains the saturation drain current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(I_{\mathrm{d},\text{sat}})$</tex> and improves the diode performance of the device. Numerical analysis results show that compared with the Con-DTMOS and Con-DTMOS with external SBD diode, the turn-on loss <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(E_{\text{on}})$</tex> and turn-off loss <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(E_{\text{off}})$</tex> for the proposed device are reduced by 56.4%/70.4% and 56.6%/69.9%, respectively. Moreover, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{d},\text{sat}}$</tex> at the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{gs}}$</tex> of 18 V for the proposed device is reduced by 74.4% and the short-circuit withstand time <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(t_{\text{SC}})$</tex> is improved by about 7.5 times. As a result, an ultra-low power loss and improved short-circuit capability is obtained for the proposed device.