Surge current management in Dynamic Reverse Bias reliability testing of WBG devices for automotive application

Efficient management of high-magnitude current spikes during Dynamic Reverse Bias (DRB) reliability testing is critical for early detection of potential issues such as gate oxide degradation in wide bandgap (WBG) devices. This paper addresses the challenges of DRB testing, particularly focusing on current surges caused by rapid dv/dt switching events in WBG devices. Compliance with AQG-324 guidelines, which require a dv/dt of 50 kV/µs, often results in significant current surges due to parasitic capacitance. These surges can reach tens of amperes, leading to excessive self-heating and potentially damaging sensitive measurement circuitry. This study introduces an innovative method to filter out capacitive displacement current spikes without affecting leakage current, reducing surge intensity by over 100 times and enabling efficient DRB testing of up to 1.5 kV WBG devices. The validation process includes simulating a Wolfspeed Power Silicon Carbide (SiC) MOSFET model in LT-Spice and conducting hardware tests on three different 1.2 kV SiC devices from Wolfspeed, Infineon, and Rohm. An optimized PCB design was employed to minimize circuit parasitics, showing good alignment between simulation and hardware testing outcomes.