A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP
An algorithm for three-layer bottleneck channel routing problem that uses ILP is proposed. The proposed algorithm determines the track and layer assignment of nets for problems with layout constraints in which pins of each net are placed on the upper boundary of the adjacent regions on both sides of the bottleneck channel. The proposed algorithm restricts the routing pattern of each net to one of three patterns by taking feasibility into account, and outputs a solution in a few seconds when the number of nets is 300.
Authors
- Satoshi Tayu
- Mathieu Molongo
- Atsushi Takahashi (ORCID: https://orcid.org/0000-0002-0757-0167)
- Makoto Minami
- Kazuya Taniguchi
- Katsuya Nishioka
Institutions
- Tokyo Institute of Technology (JP)
Publication Details
- Journal
- IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
- Published
- 2024-09-08
- DOI
- https://doi.org/10.1587/transfun.2024vlp0002
- Citations
- 7
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 1.46