A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP

An algorithm for three-layer bottleneck channel routing problem that uses ILP is proposed. The proposed algorithm determines the track and layer assignment of nets for problems with layout constraints in which pins of each net are placed on the upper boundary of the adjacent regions on both sides of the bottleneck channel. The proposed algorithm restricts the routing pattern of each net to one of three patterns by taking feasibility into account, and outputs a solution in a few seconds when the number of nets is 300.

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Publication Details

Journal
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
Published
2024-09-08
DOI
https://doi.org/10.1587/transfun.2024vlp0002
Citations
7
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
1.46
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article

A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP

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7 citations
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
VLSI and FPGA Design Techniques
1.46
article

A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP

Satoshi Tayu, Mathieu Molongo, Atsushi Takahashi, Makoto Minami, Kazuya Taniguchi, Katsuya Nishioka
article en
7 citations

Abstract

An algorithm for three-layer bottleneck channel routing problem that uses ILP is proposed. The proposed algorithm determines the track and layer assignment of nets for problems with layout constraints in which pins of each net are placed on the upper boundary of the adjacent regions on both sides of the bottleneck channel. The proposed algorithm restricts the routing pattern of each net to one of three patterns by taking feasibility into account, and outputs a solution in a few seconds when the number of nets is 300.

IEICE Transactions on Fundamentals of Electronics Communications and Computer SciencesVol. E108.A(3)
Tokyo Institute of Technology (JP)
Affordable and clean energy
Openalex Percentile: Top 18%
VLSI and FPGA Design Techniques
1.46
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