Synthesis of Two-Block Logic Circuits, Implementing the Functions of k-Valued Logic

The problem of the schematic implementation of k-valued logic functions defined by tabular representations is considered. The proposed approach is based on technologically independent optimization of the representation of the k-valued logic function in the form of a multi-valued Decision Diagram (MDD), after which the values of the arguments and values of the function are encoded by sets of Boolean variables. As a result of encoding, the k-valued function is replaced by a system of not fully defined Boolean functions. The system of Boolean functions is minimized in the BDD class of representations (Binary Decision Diagram (BDD) — binary decision diagram). It is proposed to carry out intermediate encoding of the values of a k-valued function using special encoding of neighboring leaf vertices BDD, which can lead to a reduction in the area of a two-block logic circuit implementing a k-valued logic function.