Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm2 (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7 μW, with the core power consumption at 932 nW.

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Publication Details

Journal
Electronics
Published
2024-09-06
DOI
https://doi.org/10.3390/electronics13173549
Citations
3
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.55

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article

Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application

Muh‐Tian Shiue, Yu-Fan Lo, Chih-Yao Jung
3 citations
Electronics
Analog and Mixed-Signal Circuit Design
0.55
article

Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application

Muh‐Tian Shiue, Yu-Fan Lo, Chih-Yao Jung
article en
3 citations

Abstract

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm2 (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7 μW, with the core power consumption at 932 nW.

ElectronicsVol. 13(17)
National Central University (TW)
National Applied Research Laboratories, Ministry of Science and Technology, Taiwan, Thailand Science Research and Innovation
Openalex Percentile: Top 37%
Analog and Mixed-Signal Circuit Design
0.55
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Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application — Muh‐Tian Shiue, Yu-Fan Lo, et al. · Electronics (2024) | TGRS Research Map | TGRS