MoS<sub>2</sub>/GaN Junction Field‐Effect Transistors with Ultralow Subthreshold Swing and High On/Off Ratio via Thickness Engineering for Logic Inverters

Abstract In recent years, 2D/3D heterojunction electronic devices have attracted considerable attention. As the size decreases, enhancing the speed of MOSFETs, reducing the subthreshold swing (SS), and lowering the power consumption (P) have become challenging. Therefore, in the post‐Moore era, in response to the continuation of Moore's law, junction field‐effect transistors (JFETs) based on mixed‐dimensional MoS 2 /GaN heterojunctions are proposed via thickness engineering. Accordingly, flat hetero interface and large potential barrier height of 5 eV across the heterojunction, an ultra‐low SS of 60.9 mV dec −1 (The Boltzmann limit is 60 mV dec −1 ) is achieved at V ds = 0.1 V when the MoS 2 thickness is 10 nm. Additionally, a high I on /I off ratio of 10 7 and a saturation current density (J ds ) of 0.16 µA µm −1 is achieved. As the thickness of MoS 2 increased from 6 to 16 nm, the working mode transitioned from enhancement mode to depletion mode. The depletion region across the channel is verified using computer‐aided design technology. Finally, an N‐type load inverter with a maximum voltage gain of 4 and a minimum static P of 25 nW is applied. Overall, the work provides a universal strategy for constructing a series of high‐performance transition metal dichalcogenide/GaN JFETs.

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Publication Details

Journal
Advanced Functional Materials
Published
2024-09-06
DOI
https://doi.org/10.1002/adfm.202410954
Citations
15
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
3.13

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article

MoS2/GaN Junction Field‐Effect Transistors with Ultralow Subthreshold Swing and High On/Off Ratio via Thickness Engineering for Logic Inverters

Jianru Chen, Mengmeng Yang, Zhidong Pan, Tao Zheng et al.
15 citations
Advanced Functional Materials
Advancements in Semiconductor Devices and Circuit Design
3.13
article

MoS2/GaN Junction Field‐Effect Transistors with Ultralow Subthreshold Swing and High On/Off Ratio via Thickness Engineering for Logic Inverters

Jianru Chen, Mengmeng Yang, Zhidong Pan, Tao Zheng, Dongxiang Luo, Liang Zhao, Xingfu Wang, Nengjie Huo, Wenfeng Li, Zhaoqiang Zheng, Wei Gao, Ruhong Zhou, Yiming Sun, Wenlong Chen, Jiabin Li, Li Fei, Jianming Huang, Jiahao Gao, Tu Zhao
article en
15 citations

Abstract

Abstract In recent years, 2D/3D heterojunction electronic devices have attracted considerable attention. As the size decreases, enhancing the speed of MOSFETs, reducing the subthreshold swing (SS), and lowering the power consumption (P) have become challenging. Therefore, in the post‐Moore era, in response to the continuation of Moore's law, junction field‐effect transistors (JFETs) based on mixed‐dimensional MoS 2 /GaN heterojunctions are proposed via thickness engineering. Accordingly, flat hetero interface and large potential barrier height of 5 eV across the heterojunction, an ultra‐low SS of 60.9 mV dec −1 (The Boltzmann limit is 60 mV dec −1 ) is achieved at V ds = 0.1 V when the MoS 2 thickness is 10 nm. Additionally, a high I on /I off ratio of 10 7 and a saturation current density (J ds ) of 0.16 µA µm −1 is achieved. As the thickness of MoS 2 increased from 6 to 16 nm, the working mode transitioned from enhancement mode to depletion mode. The depletion region across the channel is verified using computer‐aided design technology. Finally, an N‐type load inverter with a maximum voltage gain of 4 and a minimum static P of 25 nW is applied. Overall, the work provides a universal strategy for constructing a series of high‐performance transition metal dichalcogenide/GaN JFETs.

Advanced Functional MaterialsVol. 34(52)
Guangdong University of Technology (CN), South China Normal University (CN), Guangzhou University (CN), Guangdong Academy of Sciences (CN)
National Natural Science Foundation of China, China Postdoctoral Science Foundation, Basic and Applied Basic Research Foundation of Guangdong Province
Openalex Percentile: Top 8%
Advancements in Semiconductor Devices and Circuit Design
3.13
DOIOpen Access PDFOpenAlex
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