An Optimized HW/SW Implementation of the Vector Median Rational Hybrid Filter for Real-Time Color Image Denoising

The presence of noise in an image can significantly diminish its visual quality and adversely affect the accuracy of subsequent image processing tasks.Therefore, it is imperative to enhance image quality in real-time by eliminating disturbances introduced during the image acquisition or transmission process.This paper proposes an efficient and optimized implementation of the vector median rational hybrid filter (VMRHF) specifically tailored for real-time color image denoising.This filter is crafted to harness the capabilities of both the vector median filter and the rational operator, enabling effective noise reduction while maintaining the integrity of edges, image details, and chromaticity.However, the hybrid architecture in the VMRHF filter brings about an increase in computational complexity.To address this complexity, the filter is implemented in a Hardware/Software (HW/SW) codesign context, capitalizing on the strengths of both hardware and software components.The software component is created using the C/C++ programming language and operates on the ARM Cortex-A53 processor with a clock frequency of 1.2 GHz, while the high-level synthesis (HLS) flow is employed to develop the hardware portion, implemented as a coprocessor in the Zynq UltraScale+ XCZU9EG FPGA.Nevertheless, in the pursuit of crafting an optimized hardware architecture for VMRHF, specific directives like ARRAY_PARTITION and PIPELINE are progressively incorporated into the VMRHF C code using the Xilinx Vivado HLS tool.The interaction between the hardware and software parts is streamlined through the AXI-stream interface, facilitated by three Direct Memory Access (DMA) units for efficient data parallel transfer, thereby boosting data throughput.The VMRHF HLS design is evaluated on the embedded ZCU102 kit.The experimental outcomes illustrate that our design is capable of restoring a 256256 color image within 19 ms, reflecting a substantial 94% decrease in execution time compared to the software design.This notable improvement is achieved while upholding consistent image quality, as indicated by both objective measures such as peak signal-to-noise ratio (PSNR) and subjective assessments.These results hold true across various levels of "salt and pepper" impulsive noise.Besides, our design exhibits a power consumption of merely 4.46 watts.

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Publication Details

Journal
Traitement du signal
Published
2024-08-31
DOI
https://doi.org/10.18280/ts.410441
Citations
2
Primary Topic
Image and Signal Denoising Methods
Type
article
Field-Weighted Citation Impact
0.50
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article

An Optimized HW/SW Implementation of the Vector Median Rational Hybrid Filter for Real-Time Color Image Denoising

Ahmed Ben Atitallah
2 citations
Traitement du signal
Image and Signal Denoising Methods
0.50
article

An Optimized HW/SW Implementation of the Vector Median Rational Hybrid Filter for Real-Time Color Image Denoising

Ahmed Ben Atitallah
article en
2 citations

Abstract

The presence of noise in an image can significantly diminish its visual quality and adversely affect the accuracy of subsequent image processing tasks.Therefore, it is imperative to enhance image quality in real-time by eliminating disturbances introduced during the image acquisition or transmission process.This paper proposes an efficient and optimized implementation of the vector median rational hybrid filter (VMRHF) specifically tailored for real-time color image denoising.This filter is crafted to harness the capabilities of both the vector median filter and the rational operator, enabling effective noise reduction while maintaining the integrity of edges, image details, and chromaticity.However, the hybrid architecture in the VMRHF filter brings about an increase in computational complexity.To address this complexity, the filter is implemented in a Hardware/Software (HW/SW) codesign context, capitalizing on the strengths of both hardware and software components.The software component is created using the C/C++ programming language and operates on the ARM Cortex-A53 processor with a clock frequency of 1.2 GHz, while the high-level synthesis (HLS) flow is employed to develop the hardware portion, implemented as a coprocessor in the Zynq UltraScale+ XCZU9EG FPGA.Nevertheless, in the pursuit of crafting an optimized hardware architecture for VMRHF, specific directives like ARRAY_PARTITION and PIPELINE are progressively incorporated into the VMRHF C code using the Xilinx Vivado HLS tool.The interaction between the hardware and software parts is streamlined through the AXI-stream interface, facilitated by three Direct Memory Access (DMA) units for efficient data parallel transfer, thereby boosting data throughput.The VMRHF HLS design is evaluated on the embedded ZCU102 kit.The experimental outcomes illustrate that our design is capable of restoring a 256256 color image within 19 ms, reflecting a substantial 94% decrease in execution time compared to the software design.This notable improvement is achieved while upholding consistent image quality, as indicated by both objective measures such as peak signal-to-noise ratio (PSNR) and subjective assessments.These results hold true across various levels of "salt and pepper" impulsive noise.Besides, our design exhibits a power consumption of merely 4.46 watts.

Traitement du signalVol. 41(4)
Jouf University (SA)
Openalex Percentile: Top 35%
Image and Signal Denoising Methods
0.50
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