High‐Performance Hardware Structure of ChaCha20 Stream Cipher Based on Sparse Parallel Prefix Adder

ABSTRACT In this paper, a high‐performance and area‐efficient hardware structure of the ChaCha20 stream cipher is presented. The most complex operation in the ChaCha20 stream cipher is addition modulo 2 32 . The addition is used in the round function computations and the addition of the last round result and initial state. We use the proposed sparse parallel prefix adder for the implementation of addition modulo 2 32 , which has a low critical path delay. In the proposed structure, to reduce area consumption, we use resource sharing with minimum hardware. To increase throughput and speed, the four registers are used with two main tasks including the storing intermediate results of the round function and the break critical path delay for the pipeline of the structure. Also, based on the used registers in the structure, the computations of the last clock cycle of the previous round function and the first clock cycle from the next round function are computed concurrently. Implementation results such as delay, computation time, area, and throughput of the proposed structure in 180 nm CMOS technology and FPGA implementation on the device Xilinx Virtex‐7 XC7VX485T are achieved. The achieved results show that the design has better hardware and timing properties compared with other works.