Research and design of high-precision discrete sigma-delta modulator

The Sigma-Delta modulator for high-order structures with one-bit quantization suffers from poor stability and high quantization error. This paper studies a novel double-sampling integrator and proposes a novel log₂3-bit quantized 2^nd order discrete Sigma-Delta modulator, which is a cascaded integrator with feedback structure without feedback branch. In Matlab, construct a Simulink model of the 2^nd order Sigma-Delta modulator to verify the feasibility of double-sampling technology and a log₂3 bits quantizer in improving the performance of the modulator. Circuit design and simulation based on TSMC 180 nm CMOS process, with a power supply voltage of 3 V and a layout area of 0.128 mm² for the 2^nd order modulator. Under the condition of signal bandwidth of 20 kHz and sampling frequency of 5.12 MHz, simulation result shows that the <i>SNR</i> of the modulator reaches 96.43 dB, <i>ENoB</i> reaches 15.72 bits, and power consumption is 120.21 &mu;W.