A Third-order Noise-shaping SAR ADC using PVT-insensitive Voltage-time-voltage Converter and Mismatch-Shaping

This paper presents a third-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-time-voltage (V-T-V) converter and mismatch shaping for capacitive digital-to-analog converters (CDACs). To achieve third-order noise shaping, the error feedback (EF) structure and cascade of integrators with feed-forwards (CIFF) structure were cascaded. The amplifier used in EF and CIFF is a V-T-V converter which is insensitive to PVT variation. To implement mismatch shaping, one more CDAC is used to generate residue voltage with data-weighted averaging. The proposed ADC was designed with a 28-nm CMOS process with 1-V power supply. The SPICE simulation results show that the designed ADC has signal-to-noise and distortion ratio (SNDR) of 82.7 dB and power consumption of 435 μW, when operated with a sampling rate of 40-MS/s and oversampling ratio of 10, resulting in a Schreier figure-of-merit (FoM) of 179.4 dB.