Design of an Approximate 4-2 Compressor with Error Recovery for Efficient Approximate Multiplication

This paper introduces a novel and efficient approximate 4-2 compressor and multipliers that significantly improve overall computation accuracy with marginal hardware overhead. The proposed compressor incorporates an error recovery logic to rectify output errors under specific input conditions. As a result, the proposed multipliers, featuring this error recovery compressor, exhibit substantial improvements in normalized mean error distance (NMED) and mean relative error distance (MRED) by up to 89.8% and 97.1%, respectively, compared to existing approximate multipliers considered in this paper. Furthermore, when implemented in a 32-nm CMOS technology, the proposed designs enable noteworthy reductions of up to 25.2%, 22.9%, and 23.4% in area, power, and energy, respectively, in comparison to the alternative designs. The effectiveness of the proposed design is further validated through its application in a digital image processing algorithm.