Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board
This paper describes a first attempt to build and operate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Microscopic post-test inspections indicate that only one of the ten SiC chips on the board failed. Most of circuit-damaging cracks observed on the failed chip corresponded to micron-scale irregularly-shaped dielectric film hillock defects. The study of these defects suggests minor processing changes to eliminate this suspected root failure cause.
Authors
- Michael J. Krasowski (ORCID: https://orcid.org/0000-0001-5936-945X)
- Norman F. Prokop
- Philip G. Neudeck (ORCID: https://orcid.org/0000-0002-2968-4712)
- Dorothy Lukco (ORCID: https://orcid.org/0000-0003-3424-0320)
- Gary W. Hunter (ORCID: https://orcid.org/0000-0002-6922-7671)
- Lawrence C. Greer
- David J. Spry
- Liang-Yü Chen (ORCID: https://orcid.org/0000-0002-2981-1945)
Institutions
- Glenn Research Center (US)
Publication Details
- Journal
- Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena
- Published
- 2024-08-21
- DOI
- https://doi.org/10.4028/p-u3mieo
- Citations
- 2
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.42
Funders
- National Aeronautics and Space Administration
- Case Western Reserve University
- Aeronautics Research Mission Directorate
- Glenn Research Center
- Science Mission Directorate