Reduced Overshoots, Oscillations, and $dV/dt$ Generation in Parallel Connected SiC MOSFET Modules With Optional Active Current Balancing

Silicon Carbide <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s offer increased switching speeds, reduced filtering component sizes and lower switching losses when compared to Silicon IGBTs in power converters. However, available module current ratings, increased oscillatory switching behavior, large drain-source voltage overshoots, and high output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dV/dt$</tex-math></inline-formula> levels are all limiting factors to their adoption in medium to high-power applications. The use of inter-device inductances with switching edge skewing has previously been demonstrated as a method of limiting current imbalances when paralleling modules. This article shows that by precisely controlling the timing skews applied between modules in such arrangements, substantial overshoot, oscillation, and output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dV/dt$</tex-math></inline-formula> reductions can also be achieved. In addition, if current feedback is included, the module switching order can be varied to facilitate a fixed-skew active current balancing strategy. The mechanisms behind all of these effects are analyzed in detail, focusing on the impact of applied timing skew, and inter-device inductance on the improvements. An experimental investigation validating the current balancing, switching performance improvements, and reduced output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dV/dt$</tex-math></inline-formula> is also presented using 400 A 1.2 kV half-bridge modules, with up to 4 modules in parallel at a total load current of 1600 A.

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Publication Details

Journal
IEEE Transactions on Power Electronics
Published
2024-09-03
DOI
https://doi.org/10.1109/tpel.2024.3453438
Citations
8
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
Field-Weighted Citation Impact
1.67
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article

Reduced Overshoots, Oscillations, and $dV/dt$ Generation in Parallel Connected SiC MOSFET Modules With Optional Active Current Balancing

S.J. Finney, Sebastián Neira, Paul D. Judge, Edward L. Horsley et al.
8 citations
IEEE Transactions on Power Electronics
Silicon Carbide Semiconductor Technologies
1.67
article

Reduced Overshoots, Oscillations, and $dV/dt$ Generation in Parallel Connected SiC MOSFET Modules With Optional Active Current Balancing

S.J. Finney, Sebastián Neira, Paul D. Judge, Edward L. Horsley, Mason Parker
article en
8 citations

Abstract

Silicon Carbide <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s offer increased switching speeds, reduced filtering component sizes and lower switching losses when compared to Silicon IGBTs in power converters. However, available module current ratings, increased oscillatory switching behavior, large drain-source voltage overshoots, and high output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dV/dt$</tex-math></inline-formula> levels are all limiting factors to their adoption in medium to high-power applications. The use of inter-device inductances with switching edge skewing has previously been demonstrated as a method of limiting current imbalances when paralleling modules. This article shows that by precisely controlling the timing skews applied between modules in such arrangements, substantial overshoot, oscillation, and output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dV/dt$</tex-math></inline-formula> reductions can also be achieved. In addition, if current feedback is included, the module switching order can be varied to facilitate a fixed-skew active current balancing strategy. The mechanisms behind all of these effects are analyzed in detail, focusing on the impact of applied timing skew, and inter-device inductance on the improvements. An experimental investigation validating the current balancing, switching performance improvements, and reduced output voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$dV/dt$</tex-math></inline-formula> is also presented using 400 A 1.2 kV half-bridge modules, with up to 4 modules in parallel at a total load current of 1600 A.

IEEE Transactions on Power ElectronicsVol. 40(1)
Gamesa (Spain) (ES), University of Edinburgh (GB)
Affordable and clean energy
Openalex Percentile: Top 16%
Silicon Carbide Semiconductor Technologies
1.67
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