Efficient and Effective Neural Networks for Automatic Test Pattern Generation

Automatic Test Pattern Generation (ATPG) algorithms such as FAN and PODEM heavily rely on a backtracing step to explore the search space. Conventional implementations often use a single metric such as a testability measure to guide backtracing. Recently, Neural Network (NN) models were proposed which combine multiple metrics to make a better backtrace decision. This paper identifies two fundamental, unresolved issues for effective and efficient use of NNs for ATPG: (1) portability of the NN model across different levels of a combinational circuit; (2) significant runtime overhead when using the NN model in backtrace decisions of each gate. To address these issues, a hybrid approach is proposed which builds and applies the NN model to only selected levels of the circuit. Guidelines to select the level and to train circuits are also discussed in this context. Also, a lookup technique is proposed to reuse the results of prior inferences at each gate to further accelerate the runtime.

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Publication Details

Published
2024-09-03
DOI
https://doi.org/10.1145/3670474.3685939
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Efficient and Effective Neural Networks for Automatic Test Pattern Generation

L. Zhang, Azadeh Davoodi
VLSI and Analog Circuit Testing
article

Efficient and Effective Neural Networks for Automatic Test Pattern Generation

L. Zhang, Azadeh Davoodi
article en

Abstract

Automatic Test Pattern Generation (ATPG) algorithms such as FAN and PODEM heavily rely on a backtracing step to explore the search space. Conventional implementations often use a single metric such as a testability measure to guide backtracing. Recently, Neural Network (NN) models were proposed which combine multiple metrics to make a better backtrace decision. This paper identifies two fundamental, unresolved issues for effective and efficient use of NNs for ATPG: (1) portability of the NN model across different levels of a combinational circuit; (2) significant runtime overhead when using the NN model in backtrace decisions of each gate. To address these issues, a hybrid approach is proposed which builds and applies the NN model to only selected levels of the circuit. Guidelines to select the level and to train circuits are also discussed in this context. Also, a lookup technique is proposed to reuse the results of prior inferences at each gate to further accelerate the runtime.

University of Wisconsin–Madison (US)
Affordable and clean energy
Openalex Percentile: Top 86%
VLSI and Analog Circuit Testing
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