A Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

This paper presents a low drop-out (LDO) regulator with feed-forward ripple cancellation (FFRC) technique, utilizing a capacitively coupled method. Power supply rejection (PSR) is identified as one of the most critical specifications, alongside performance over a wide frequency range and at maximum load current. The paper presents a technique to enhance the PSR of the LDO and demonstrates the feasibility and relevance of these methods through equation derivation. The proposed LDO is designed using a 0.18 µm process, with input voltage specifications ranging from 1.3 V to 1.8 V, an output voltage of 1.2 V, and a static current consumption of 38.6 µA, utilizing an external regulator capacitor of 1 µF. This design achieves a PSR of -60 dB at load currents ranging from 1 mA to 40 mA. It also extends the bandwidth when the LDO is supplied with larger load currents, achieving a PSR of -73 dB at a frequency of 500 kHz and maintaining a PSR of -61 dB or more at 1 MHz.

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Publication Details

Journal
IEEE Nanotechnology Magazine
Published
2024-09-03
DOI
https://doi.org/10.1109/mnano.2024.3436408
Citations
2
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.37

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article

A Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

Shao‐Ku Kao, Chien‐Hung Liao, Wen-Shuo Chang, Yi-He Chiu
2 citations
IEEE Nanotechnology Magazine
Analog and Mixed-Signal Circuit Design
0.37
article

A Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

Shao‐Ku Kao, Chien‐Hung Liao, Wen-Shuo Chang, Yi-He Chiu
article en
2 citations

Abstract

This paper presents a low drop-out (LDO) regulator with feed-forward ripple cancellation (FFRC) technique, utilizing a capacitively coupled method. Power supply rejection (PSR) is identified as one of the most critical specifications, alongside performance over a wide frequency range and at maximum load current. The paper presents a technique to enhance the PSR of the LDO and demonstrates the feasibility and relevance of these methods through equation derivation. The proposed LDO is designed using a 0.18 µm process, with input voltage specifications ranging from 1.3 V to 1.8 V, an output voltage of 1.2 V, and a static current consumption of 38.6 µA, utilizing an external regulator capacitor of 1 µF. This design achieves a PSR of -60 dB at load currents ranging from 1 mA to 40 mA. It also extends the bandwidth when the LDO is supplied with larger load currents, achieving a PSR of -73 dB at a frequency of 500 kHz and maintaining a PSR of -61 dB or more at 1 MHz.

IEEE Nanotechnology MagazineVol. 18(5)
Chang Gung University (TW), Linkou Chang Gung Memorial Hospital (TW)
Chang Gung Memorial Hospital, Linkou
Zero hunger
Openalex Percentile: Top 44%
Analog and Mixed-Signal Circuit Design
0.37
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A Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique — Shao‐Ku Kao, Chien‐Hung Liao, et al. · IEEE Nanotechnology Magazine (2024) | TGRS Research Map | TGRS