Topology and Control of Multiport DC Circuit Breaker Integrating Current-Limiting and Fast Fault Clearing Capabilities

To address the technical challenges of DC fault clearing in DC grid, a multiport DC circuit breaker (DCCB) integrating current-limiting and fast fault clearing capabilities is proposed. Due to the topology design of the H-bridge LCSs and the additional bridge arm provided in the H-bridge component for connecting to the DC bus, the proposed DCCB possesses the capability to clear DC bus faults. Three control strategies were designed, including energization, fault interruption following current limiting and reset following current limiting. The proposed topology realizes a large reduction of peak current value by employing a current limiting component. The time required for fault clearing is minimized by implementing a bypass component. The proposed control strategy enables the pre-charge of circuit breaker capacitor by multiplexing a portion of the topology loop. The operating sequence of circuit breaker is optimized through a two-step process: preliminary fault judgment and secondary confirmation. This process further reduces the current value at the break time. A five-terminal DC grid simulation model is built in PSCAD/EMTDC, and various operating conditions of circuit breakers are simulated and verified. The results show that the proposed multiport DCCB can quickly and reliably clear faults in multiple DC lines and DC bus, reduce the peak current value, and minimize the time required for fault interruption under all working conditions.