A Unified Sampling Mechanism to Control Average and Peak Current in a Buck Converter Under Trailing-Edge Modulation

Traditional digital implementation of average current-mode control (CMC) digitizes current loop and voltage loop. Accuracy of average current tracking depends on the sampled value of the inductor current. Existing uniformly sampled digital average CMC techniques use leading-edge modulation or dual-edge modulation and they are not easily configurable to control the peak inductor current. Moreover, existing peak CMC under leading-edge modulation is prone to noise. This article proposes a simple and robust sampling mechanism that can be configured to implement digital average CMC or peak CMC under trailing-edge modulation without changing the fundamental structure of the controller. Furthermore, the proposed peak CMC is insensitive to noise and stable even with a duty greater than 0.5. Approximate discrete-time modeling approach is considered to model the proposed mechanism. Impacts of system's parasitics on the sampling mechanism are analyzed and they are found to be insignificant. The proposed average and peak current control schemes are validated with MATLAB simulations and experimental results. The proposed sampling mechanism can be easily extended for other digital current-mode controlled converters.