A Scalable Multi-FPGA Platform for Hybrid Intelligent Optimization Algorithms

The Intelligent Optimization Algorithm (IOA) is widely focused due to its ability to search for approximate solutions to the NP-Hard problem. To enhance applicability to practical scenarios and leverage advantages from diverse intelligent optimization algorithms, the Hybrid Intelligent Optimization Algorithm (H-IOA) is employed. However, IOA typically requires numerous iterations and substantial computing resources, resulting in poor execution efficiency. In complex optimization scenarios, IOA traditionally relies on population partitioning and periodic communication, highlighting the feasibility and necessity of parallelization. To address the challenges above, this paper proposes a general hardware design approach for H-IOA based on multi-FPGA. The approach includes the hardware architecture of multi-FPGA, inter-board communication protocols, population storage strategies, complex hardware functions, and parallelization methodologies, which enhance the computing capabilities of H-IOA. To validate the proposed approach, a case study is conducted, in which an H-IOA integrating genetic algorithm (GA), a simulated annealing algorithm (SA), and a pigeon-inspired optimization algorithm (PIO) are implemented on a multi-FPGA platform. Specifically, the flexible job-shop scheduling problem (FJSP) is employed to verify the potential in industrial applications. Two Xilinx XC6SLX16 FPGA chips are used for hardware implementation, encoded in VHDL, and an AMD Ryzen 7 5800U was used for the software implementation of Python programs (version 3.12.4). The results indicate that hardware implementation is 13.4 times faster than software, which illustrates that the proposed approach effectively improves the execution performance of H-IOA.