A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-Bit Conversion/Cycle Time-Domain Comparator

This brief presents a 0.6 V 4-MS/s 2-bit conversion/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator which is employed to suppress the input referred noise. The VCO-based comparison requires many oscillation cycles to amplify phase differences between VCOs if the input voltage difference is small. In this design, therefore, a 2-bit conversion/cycle scheme is adopted to optimize the ADC sampling rate and an asynchronous timing controller is applied to optimize the conversion time. The proposed SAR ADC is fabricated in 65-nm CMOS technology. At the 0.6 V supply voltage and the 4-MS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.42 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.58/−0.79 LSB and +0.52/−0.75 LSB, respectively. The figure of merits (FoM) is 6.59 fJ/conversion-step with the power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15.93~\mu $ </tex-math></inline-formula> W.