Effects of Grain Size on Various Electrical Trap Extraction Methods in Low-Temperature Polysilicon Thin Films

This study investigated the effect of grain size on trap extraction methods by characterizing metal-oxide–semiconductor capacitors (MOSCAPs) and thin-film transistors (TFTs) composed of low-temperature polysilicon (LTPS) thin films with two different grain sizes. The near-midgap interface state density, with minimal interference from grain boundary traps, was examined using capacitance-voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</i>)-based approaches, including quasi-static (QS) and conductance methods, in MOSCAPs. However, noise and a limited measurement range hindered the distinction between the grain boundary trap densities of the samples. When the single-pulse charge pumping (SPCP) method was applied to the TFTs, only interface states were detected using a small pulsewidth. The response of grain boundary traps became stronger as the pulsewidth increased, which was evidenced by a higher trap density with smaller grain sizes. The mobility method, which utilized temperature-dependent mobility changes in the TFTs, effectively distinguished between the LTPS samples by directly determining the grain boundary trap density. The simultaneous use and comparison of these various extraction methods will be helpful in extracting and understanding the traps in polycrystalline channels.