SmartSiC™ Substrates: A Boon to Drain Metallization Process
We present results of epitaxial characterization and benchmarking of Silicon Carbide (SiC) epitaxial layers grown on both 6-inch commercially available SiC substrate and on SOITEC’s new generation SmartSiC TM substrate. Multi wafer reactor was utilized to avoid run-to-run variation. Schottky Barrier Diodes (SBD) and electrical test vehicles were fabricated to extract ideality factor, barrier height and ohmic contact resistance for benchmarking.
Authors
- Navab Singh (ORCID: https://orcid.org/0000-0003-3299-9093)
- W. Schwarzenbach (ORCID: https://orcid.org/0000-0003-2821-0854)
- Surasit Chung
- L. K. Bera (ORCID: https://orcid.org/0000-0003-3171-4463)
- Qin Gui Roth Voo
- Ionut Radu (ORCID: https://orcid.org/0000-0002-6839-1015)
- Abdul Hannan Yeo (ORCID: https://orcid.org/0000-0003-2375-5732)
- Umesh Chand (ORCID: https://orcid.org/0000-0002-9302-5965)
- Shiv Kumar (ORCID: https://orcid.org/0000-0003-0655-9561)
- Hüseyin Çakmak (ORCID: https://orcid.org/0000-0002-1463-7606)
- Hanlin Xie (ORCID: https://orcid.org/0000-0002-1974-2018)
- Loic Kabelaan
- Sonia Anton Hillary Ratranaj
- Amelie Thomas
- Vudumula Pavan Reddy
Institutions
- Soitec (France) (FR)
Publication Details
- Journal
- Materials science forum
- Published
- 2024-08-21
- DOI
- https://doi.org/10.4028/p-vhvc04
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00