Design and Implementation of Optimized PCI Express Physical Layer for High-Speed and Low-Latency Data Transfer

The PCIe (Peripheral Component Interconnect Express) Protocol is crucial for establishing high-speed data communication between computer peripherals, such as graphics cards and network cards etc. This communication protocol is transmitting data in packet format, with each packet containing both data and destination address and other essential information for accurate data delivery. This paper focused on Physical Layer to achieve High-Speed Data Transmission by reducing delay parameter. To minimize disturbances and enhance reliability, the physical layer uses scrambling technique and an 8b – 10b encoding technique is used for synchronization and error detection. Additionally, SIPO and PISO converts data format to improve efficiency and accuracy. The design is implemented using the Cadence compiler targeting 45nm process technology. This design is delay efficient resulting in path delay of 5.0ns and the operating frequency of 200MHz, power consumption of 1.2mw and an area of 1999µm².