A 6.5-to-8-GHz Cascaded Dual-Fractional- <i>N</i> Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference

This work presents a 6.5-to-8-GHz cascaded dual-fractional-N digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer-N mode and an integrated jitter of 190.8 fs in fractional-N mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of −242.9 dB. The fractional spur at near-integer channel is as low as −52.79 dBc, and the reference spur is −72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm2 core area.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2024-08-30
DOI
https://doi.org/10.1109/jssc.2024.3447021
Citations
7
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
Field-Weighted Citation Impact
1.46

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article

A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference

Atsushi Shirane, Yuang Xiong, Yuncheng Zhang, Ashbir Aviat Fadila et al.
7 citations
IEEE Journal of Solid-State Circuits
Advancements in PLL and VCO Technologies
1.46
article

A 6.5-to-8-GHz Cascaded Dual-Fractional- N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference

Atsushi Shirane, Yuang Xiong, Yuncheng Zhang, Ashbir Aviat Fadila, Bangan Liu, Waleed Madany, Kenichi Okada, Junjun Qiu, Zheng Sun, Dingxin Xu, Hóngyè Huáng, Zezheng Liu, Wenqian Wang
article en
7 citations

Abstract

This work presents a 6.5-to-8-GHz cascaded dual-fractional-N digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer-N mode and an integrated jitter of 190.8 fs in fractional-N mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of −242.9 dB. The fractional spur at near-integer channel is as low as −52.79 dBc, and the reference spur is −72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm2 core area.

IEEE Journal of Solid-State CircuitsVol. 60(3)
Tokyo Institute of Technology (JP)
Ministry of Internal Affairs and Communications, Japan Science and Technology Agency, National Institute of Information and Communications Technology
Openalex Percentile: Top 18%
Advancements in PLL and VCO Technologies
1.46
DOIOpen Access PDFOpenAlex
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