A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator

This brief proposes a parallel multiresidual (PMR) integrator to enhance the noise-shaping (NS) effect for successive approximation register (SAR) analog-to-digital converter (ADC). The PMR employs passive integrators in parallel to simultaneously integrate the average result of the multiple sequential residual voltages. The proposed PMR technique provides an alternative scheme to enhance the NS rather than increasing the order of the integrator to suppress the instability and power. A prototype 7-bit second-order NS-SAR ADC is designed and simulated in a 130-nm CMOS process. PMR increases the effective number of bits (ENOBs) to 10.6 bit, which enhances the NS effect of 3.6 bit. It achieves a peak signal-to-noise and distortion ratio (SNDR) of 65.84 dB over a bandwidth of 1.3 kHz at the oversampling ratio (OSR) of 16.

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Publication Details

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2024-08-30
DOI
https://doi.org/10.1109/tvlsi.2024.3447740
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.00

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article

A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator

Longbin Zhu, Siyuan Xie, Jia‐nan Zheng, Zhijun Zhou et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog and Mixed-Signal Circuit Design
article

A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator

Longbin Zhu, Siyuan Xie, Jia‐nan Zheng, Zhijun Zhou, Keping Wang, Zhengtao Zhu, Yang Zhou, Wenjie Wang, Fanyi Meng, Risheng Su, Jihong Li
article en

Abstract

This brief proposes a parallel multiresidual (PMR) integrator to enhance the noise-shaping (NS) effect for successive approximation register (SAR) analog-to-digital converter (ADC). The PMR employs passive integrators in parallel to simultaneously integrate the average result of the multiple sequential residual voltages. The proposed PMR technique provides an alternative scheme to enhance the NS rather than increasing the order of the integrator to suppress the instability and power. A prototype 7-bit second-order NS-SAR ADC is designed and simulated in a 130-nm CMOS process. PMR increases the effective number of bits (ENOBs) to 10.6 bit, which enhances the NS effect of 3.6 bit. It achieves a peak signal-to-noise and distortion ratio (SNDR) of 65.84 dB over a bandwidth of 1.3 kHz at the oversampling ratio (OSR) of 16.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 32(11)
Tianjin University (CN), Southeast University (CN)
Fundamental Research Funds for the Central Universities
Openalex Percentile: Top 87%
Analog and Mixed-Signal Circuit Design
DOISourceOpenAlex
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