Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon

In this work, we report InAsP-based dislocation filter layers (DFLs) for InP heteroepitaxy on CMOS-standard (001) Si substrates, demonstrating a threading dislocation density of 3.7 × 107 cm−2. The strain introduced by InAsP induces dislocation bending at the InAsP/InP interface, thereby facilitating the reaction and annihilation of dislocations during their lateral glide. Concurrently, the InP spacer exhibits tensile strain, leading to the formation of stacking faults (SFs). With a comprehensive analysis utilizing x-ray diffraction, electron channeling contrast imaging, and transmission electron microscopy, the effects of DFL-induced strain on dislocations and SFs are investigated. Fine-tuning the strain conditions allowed low-dislocation-density while SF-suppressed, anti-phase boundary free InP on Si. This work, therefore, provides a useful buffer engineering scheme for monolithic integration of InP-based electronic and photonic devices onto the industry-standard silicon platform.

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Publication Details

Journal
Applied Physics Letters
Published
2024-08-19
DOI
https://doi.org/10.1063/5.0219507
Citations
4
Primary Topic
Semiconductor Quantum Structures and Devices
Type
article
Field-Weighted Citation Impact
1.35

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article

Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon

T. Baron, Bogdan‐Petrin Ratiu, Hui Jia, M. Martin et al.
4 citations
Applied Physics Letters
Semiconductor Quantum Structures and Devices
1.35
article

Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon

T. Baron, Bogdan‐Petrin Ratiu, Hui Jia, M. Martin, Mingchu Tang, Ka Ming Wong, Zhao Yan, Huiyun Liu, Shangfeng Liu, Qiang Li
article en
4 citations

Abstract

In this work, we report InAsP-based dislocation filter layers (DFLs) for InP heteroepitaxy on CMOS-standard (001) Si substrates, demonstrating a threading dislocation density of 3.7 × 107 cm−2. The strain introduced by InAsP induces dislocation bending at the InAsP/InP interface, thereby facilitating the reaction and annihilation of dislocations during their lateral glide. Concurrently, the InP spacer exhibits tensile strain, leading to the formation of stacking faults (SFs). With a comprehensive analysis utilizing x-ray diffraction, electron channeling contrast imaging, and transmission electron microscopy, the effects of DFL-induced strain on dislocations and SFs are investigated. Fine-tuning the strain conditions allowed low-dislocation-density while SF-suppressed, anti-phase boundary free InP on Si. This work, therefore, provides a useful buffer engineering scheme for monolithic integration of InP-based electronic and photonic devices onto the industry-standard silicon platform.

Applied Physics LettersVol. 125(8)
Institut polytechnique de Grenoble (FR), Centre National de la Recherche Scientifique (FR), Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR), CEA Grenoble (FR), Laboratoire d'Électronique des Technologies de l'Information (FR), University College London (GB), Cardiff University (GB), Université Grenoble Alpes (FR)
Engineering and Physical Sciences Research Council
Industry, innovation and infrastructure
Openalex Percentile: Top 20%
Semiconductor Quantum Structures and Devices
1.35
DOIOpen Access PDFOpenAlex
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