YOLO-RRL: A Lightweight Algorithm for PCB Surface Defect Detection

Printed circuit boards present several challenges to the detection of defects, including targets of insufficient size and distribution, a high level of background noise, and a variety of complex types. These factors contribute to the difficulties encountered by PCB defect detection networks in accurately identifying defects. This paper proposes a less-parametric model, YOLO-RRL, based on the improved YOLOv8 architecture. The YOLO-RRL model incorporates four key improvement modules: The following modules have been incorporated into the proposed model: Robust Feature Downsampling (RFD), Reparameterised Generalised FPN (RepGFPN), Dynamic Upsampler (DySample), and Lightweight Asymmetric Detection Head (LADH-Head). The results of multiple performance metrics evaluation demonstrate that YOLO-RRL enhances the mean accuracy (mAP) by 2.2 percentage points to 95.2%, increases the frame rate (FPS) by 12%, and significantly reduces the number of parameters and the computational complexity, thereby achieving a balance between performance and efficiency. Two datasets, NEU-DET and APSPC, were employed to evaluate the performance of YOLO-RRL. The results indicate that YOLO-RRL exhibits good adaptability. In comparison to existing mainstream inspection models, YOLO-RRL is also more advanced. The YOLO-RRL model is capable of significantly improving production quality and reducing production costs in practical applications while also extending the scope of the inspection system to a wide range of industrial applications.