Early-Stage Reliability Evaluation of Passivation Stack and Termination Designs in SiC MPS Diodes

We present an early-stage reliability evaluation approach to assess the impact of surface charges in the passivation overcoat (PO) film layers. This is obtained by applying a so-called accelerated wafer-level reverse breakdown voltage stability test in combination with wafer-level static and Van der Pauw measurements. Here, we applied this approach on 4H-SiC merged PiN Schottky diodes with a single-zone junction termination extension fabricated by using different border doses and PO stacks. Accordingly, the correlation between design parameters and the influence of surface charges can be quickly identified, leading to reduced cycle time and enhanced product reliability by optimizing the design of the JTE parameters already in the development phase. This study supports diodes and MOSFETs product manufacturing with an efficient optimization approach to address design and process impacts toward acquiring long-term lifetime demanded in automotive and industrial applications.