A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum

This article presents a fully integrated low-dropout (LDO) regulator that offers high power-supply rejection (PSR) across the full frequency spectrum. The proposed domino-like-buffered (DLB) design, which features multistage-cascaded buffers that progressively drive segmented pass transistors, significantly elevates non-dominant poles beyond the unity-gain frequency, thereby addressing stability challenges posed by the small output capacitor (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {L}}$ </tex-math></inline-formula>). This advancement allows the full exploitation of the high PSR advantage inherent in the output-pole-dominant (OPD) LDO, even with a compact on-chip <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {L}}$ </tex-math></inline-formula>. Compared to traditional LDO designs, our approach can loosen the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {L}}$ </tex-math></inline-formula> requirement by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.4\times $ </tex-math></inline-formula> to maintain the same phase margin (PM). The chip, fabricated in a 28-nm CMOS process, is designed to supply up to 10 mA of load current with a typical dropout voltage of 200 mV. Performance tests reveal an undershoot and overshoot of 51 and 50 mV, respectively, for a 9.8-mA load step. Despite its small on-chip <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {L}}$ </tex-math></inline-formula> of 50 pF, the DLB LDO demonstrates a worst case PSR of –28 dB across frequencies from 10 Hz to 1 GHz. It also occupies a minimal silicon area of 0.012 mm2, including the on-chip <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {L}}$ </tex-math></inline-formula>.