An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS

This article presents a high-resolution and energy-efficient pipelined-successive-approximation-register (SAR) capacitance-to-digital converter (CDC). The converter uses a two-stage SAR analog-to-digital converter (ADC) and a residue amplifier (RA) to effectively convert the input signal. To mitigate the impact of kT/C noise during the sampling process, an enhanced kT/C noise cancellation technique is used within a pipelined-SAR architecture. In addition, an innovative incomplete-settling-based correlated-level-shifting (ISCLS) technique is proposed to achieve an equivalent open-loop gain of over 80 dB, thereby enhancing power efficiency and amplification accuracy. Furthermore, a background calibration loop is proposed to track PVT changes and ensure high-precision amplification under PVT variations to ensure PVT stability. The proposed CDC is implemented in a 22-nm CMOS process. The prototype achieves a resolution of 37.12 aF under 384-fF input capacitance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.71~\mu $ </tex-math></inline-formula>W, resulting in a Walden figure-of-merit (FoMw) of 7.9 fJ/conv.-step, which represents more than a twofold improvement compared with previous sub-fF resolution CDCs.